Category:LNCS 2147

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Lecture Notes in Computer Science, Volume 2147

Articles in category "LNCS 2147"

There are 73 articles in this category.

A A Data Re-use Based Compiler Optimization for FPGAs A Digit-Serial Structure for Reconfigurable Multipliers A Generic Library for Adaptive Computing Environments A Music Synthesizer on FPGA A New Placement Method for Direct Mapping into LUT-Based FPGAs A Reconfigurable Approach to Packet Filtering A Reconfigurable Embedded Input Device for Kinetically Challenged Persons A System on Chip for Power Line Communications According to European Home Systems Specifications A n-Bit Reconfigurable Scalar Quantiser Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing An Approach to Real-Time Visualization of PIV Method with FPGA An Emulator for Exploring RaPiD Configurable Computing Architectures An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars Arithmetic Operation Oriented Reconfigurable Chip: RHW B Bubble Partitioning for LUT-Based Sequential Circuits Building Asynchronous Circuits with JBits C CRISP: A Template for Reconfigurable Instruction Set Processors Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux Chip-Based Reconfigurable Task Management Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines Configuration Caching and Swapping D Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware

D cont. Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware Dynamically Reconfigurable Cores E Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures Evaluation of an FPGA Implementation of the Discrete Element Method F FGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits FPGA Resource Reduction Through Truncated Multiplication FPGA-Based Discrete Wavelet Transforms System FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding Field-programmable logic and applications: 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001: proceedings G Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays Generative Development System for FPGA Processors with Active Components Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs H Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach I Implementation of (Normalised) RLS Lattice on Virtex Implementation of a NURBS to B'ezier Conversor with Constant Latency Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic Initial Analysis of the Proteus Architecture J JBitsTM Implementations of the Advanced Encryption Standard (Rijndael) L Loop Tiling for Reconfigurable Accelerators M Macrocell Architectures for Product Term Embedded Memory Arrays Memory Synthesis for FPGA-Based Reconfigurable Computers Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders Multiple Stereo Matching Using an Extended Architecture

P Parameterized Function Evaluation for FPGAs Placing, Routing, and Editing Virtual FPGAs Prototyping Framework for Reconfigurable Processors PuMA : From Behavioral Specification to Multi-FPGA-Prototype R Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits Real Time Morphological Image Contrast Enhancement in Virtex FPGA Reconfigurable Breakpoints for Co-debug Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems Reconfigurable Router Modules Using Network Protocol Wrappers Run-Time Optimized Reconfiguration Using Instruction Forecasting Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers S Secure Configuration of Field Programmable Gate Arrays Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm Static Profile-Driven Compilation for FPGAs Synthesizing RTL Hardware from Java Byte Codes System Level Tools for DSP in FPGAs T Task-Parallel Programming of Reconfigurable Systems Technology Trends and Adaptive Computing The MOLEN rho mu-Coded Processor The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems Tightly Integrated Placement and Routing for FPGAs U Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification V Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver X X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor